3.1 SAMA5D2-XULT Development Kit

The SAMA5D2-XULT development kit is built on a 6-layer PCB. The board features a SAMA5D27/BGA289 MPU and two 2-Gbit Micron DDR3L-SDRAM devices (Part No: MT41K128M16JT-125:K).

Figure 3-1. SAMA5D2C-XULT Development Kit
Figure 3-2. SAMA5D2-XULT Layer 1 (Top)

The layout example in the above figure shows the top layer of the board focused on the DDR3-SDRAM routing. Part of the address signals and the differential clock is present on the top layer, with the mentioned trace width and minimum clearance. These values are equal to or above the minimum required. There is also a 30 mils clearance between the control/command and data signals, above the minimum required.

Figure 3-3. SAMA5D2-XULT Layer 6 (Bottom)

The above figure shows the bottom layer of the DDR3-SDRAM layout. Signals from two data lanes are being routed on the bottom layer, belonging to data lane 2 (D16-D23) and data lane 0 (D0-D7), including their respective DQS/DQSn and DQM signals. Trace width used is 5 mils, and the smallest clearance is 9 mils, both values exceeding the minimum required. These traces are tightly matched, the maximum mismatch length not exceeding 7 mils, well below the maximum allowed.
Figure 3-4. SAMA5D2-XULT Layer 5 (VDD)

The above figure shows layer 5 of the board, used as a power plane. The highlighted region covers the traces belonging to the DDR3-SDRAM routing and serves as a reference plane for the impedance matching of the bottom traces. Also, it contains no splits across any high-speed signal.

The trace impedance for top or bottom layers is calculated using the impedance formula (according to Standard IPC-2141) for a microstrip line:

Equation 1

Z0(Ω)=87√εr+1.41ln[5.98H(0.8W+T)]

Where εr is the dielectric constant, H is the dielectric height, W is the trace width and T the trace thickness.

In our case (available in the table SAMA5D2-XULT Detailed PCB Stack-up):

  • εr = 3.95 for FR-4 dielectric
  • H = 3.8207 mils between bottom layer (layer 6) and power plane (layer 5)
  • W = 5 mils width for bottom traces
  • T = 1.87 mils copper thickness.
Using the above parameters, the trace impedance is calculated to be Z0 = 51.18 Ω, covered by the ±10% tolerance.
Figure 3-5. SAMA5D2-XULT PCB Stacking
Table 3-1. SAMA5D2-XULT Detailed PCB Stack-up
Layer NameTypeMaterialThickness [mm]Thickness [mil]Dielectric MaterialDielectric Constant
Top OverlayOverlay–––––
Top SolderSolder Mask/CoverlaySurface Material0.010160.4Solder Resist3.5
TOPSignalCopper0.04751.87––
Dielectric1DielectricCore0.097053.8207FR-43.95
GND2SignalCopper0.030481.2––
Dielectric2DielectricCore0.13.937FR-43.85
INT3SignalCopper0.030481.2––
Dielectric3DielectricCore0.9348436.8047FR-43.99
INT4SignalCopper0.030481.2––
Dielectric4DielectricCore0.13.937FR-43.85
VCC5SignalCopper0.030481.2––
Dielectric5DielectricCore0.097053.8207FR-43.95
BOTTOMSignalCopper0.04751.87––
Bottom SolderSolder Mask/CoverlaySurface Material0.010160.4Solder Resist3.5
Bottom OverlayOverlay–––––