3.2 SAMA5D2-PTC-EK Development Kit

The SAMA5D2-PTC-EK is a development kit built on an 8-layer PCB. The board features a SAMA5D27/BGA289 MPU and two 2-Gbit Winbond DDR2-SDRAM devices (Part No.: W972GG6KB-25).

The layout example in the above figure shows the top layer of the board focused on the DDR2-SDRAM routing. Some of the address signals and the differential clock are present on the top layer, with the mentioned trace width and minimum clearance. These values are equal to or above the minimum required. There is also a 10 mils clearance between the CK/CKn signals and any other signal, above the minimum required.

The layout example in the above figure shows the bottom layer of the DDR2-SDRAM layout. Signals from two data lanes are being routed on the bottom layer, belonging to data lane 2 (D16-D23) and data lane 0 (D0-D7), including their respective DQS/DQSn and DQM signals. Trace width used is 5 mils, and the clearance is 10 mils, both values exceeding the minimum required. On very short distances (typically the route a path needs to take to escape a dense BGA area), the clearance may go slightly below the minimum required. This is acceptable for dense designs only and shall be applied only if no other solution exists. These signals are also length-matched.

The above figure shows layer 5 of the board, used as a power plane. The highlighted region covers the traces belonging to the DDR2-SDRAM routing and serves as a reference plane for the impedance matching of the signals from layer 6 (see layer stack-up). Also, it contains no splits across any high-speed signal.

The trace impedance for inner layer 6 (see the figure below), which is used as signal layer, is calculated using the impedance formula (according to Standard IPC-2141) for an asymmetric stripline:

Equation 2

Z₀(Ω)=$\frac{80}{\sqrt[]{{\epsilon }_r}}\mathit{ln}\left[\frac{1.9(2H+T)}{0.8W+T}\right]\left[1-\frac{H}{4H_1}\right]$

Where ε_r is the dielectric constant, H1 is the dielectric height below the signal layer, H is the dielectric height above the signal layer, W is the trace width and T the trace thickness.

In our case (available in the table SAMA5D2-PTC-EK Detailed PCB Stack-up):

• ε_r = 4.5 for FR-4 dielectric
• H1 = 13.8 mils below layer 6
• H = 5.12 mils above layer 6
• W = 5 mils trace width
• T = 1.38 mils copper thickness

Using the above parameters, the trace impedance is calculated to be Z0 = 48.26 Ω, covered by the ±10% tolerance.

Applying Equation 1 for traces on the top or bottom layer, for the above parameters and a dielectric height H = 3.63 mils, results in a near perfect 49.92 Ω trace impedance.