22.8.7 Software Trigger Control

Name:	SWTRIGCTRL
Offset:	0x10
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	SWTRIGn[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SWTRIGn[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – SWTRIGn[15:0] Channel n Software Trigger [n = 15..0]

This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a ‘1’ to it. See CHSTATUS in the DMAC Register Summary from Related Links.

This bit is set if CHSTATUS.PEND is already ‘1’ when writing a ‘1’ to that bit. See CHSTATUS in the DMAC Register Summary from Related Links.

Writing a ‘0’ to this bit will clear the bit.

Writing a ‘1’ to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. See CHSTATUS in the DMAC Register Summary from Related Links.