11.10.1 Cache Type

Name: TYPE
Offset: 0x00
Reset: 0x000012D2
Property: R

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   CLSIZE[2:0]CSIZE[2:0] 
Access RRRRRR 
Reset 010010 
Bit 76543210 
 LCKDOWNWAYNUM[1:0]RRPLRUPRANDPGCLKAP 
Access RRRRRRRR 
Reset 11010010 

Bits 13:11 – CLSIZE[2:0] Cache Line Size

This field configures the Cache Line Size.
ValueNameDescription
0x2 CLSIZE_16B Cache Line Size is 16 bytes
0x3-0x7 — Reserved

Bits 10:8 – CSIZE[2:0] Cache Size

This bit field configures the cache size.
ValueNameDescription
0x0 CSIZE_1KB Cache Size is 1 KB
0x1 CSIZE_2KB Cache Size is 2 KB
0x2 CSIZE_4KB Cache Size is 4 KB
0x3-0x7 — Reserved

Bit 7 – LCKDOWN Lock Down Supported

Writing a ‘0’ to this bit disables the Lock Down feature.

Writing a ‘1’ to this bit enables the Lock Down feature.

Bits 6:5 – WAYNUM[1:0] Number of Way

This bit field configures the mapping of the cache.
ValueNameDescription
0x0 DMAPPED Direct Mapped Cache
0x1 ARCH2WAY 2-WAY set associative
0x2 ARCH4WAY 4-WAY set associative
0x3 ARCH8WAY 8-WAY set associative

Bit 4 – RRP Round Robin Policy Supported

Writing a ‘0’ to this bit disables Round Robin Policy.

Writing a ‘1’ to this bit enables Round Robin Policy.

Bit 3 – LRUP Least Recently Used Policy Supported

Writing a ‘0’ to this bit disables the Least Recently Used Policy Supported.

Writing a ‘1’ to this bit enables the Least Recently Used Policy Supported.

Bit 2 – RANDP Random Selection Policy Supported

Writing a ‘0’ to this bit disables the Random Selection Policy Supported.

Writing a ‘1’ to this bit enables the Random Selection Policy Supported.

Bit 1 – GCLK Dynamic Clock Gating

Writing a ‘0’ to this bit disables the Dynamic Clock Gating feature.

Writing a ‘1’ to this bit enables the Dynamic Clock Gating feature.

Bit 0 – AP Access Port Access Allowed

Writing a ‘0’ to this bit disables the Access Port Access Allowed.

Writing a ‘1’ to this bit enables the Access Port Access Allowed.