1 Silicon Issue Summary

Legend
-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. B(1)
DeviceWriting the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration ValuesX
ACCoupling Through AC PinsX
AC Interrupt Flag Not Set Unless Interrupt is EnabledX
False Triggers May Occur Under Certain ConditionsX
False Triggering When Sweeping Negative Input of the AC When the Low-Power Mode is DisabledX
ADCADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty CycleX
Pending Event Stuck When Disabling the ADCX
ADC Interrupt Flags Cleared When Reading RESHX
Changing ADC Control Bits During Free-Running Mode not WorkingX
One Extra Measurement Performed After Disabling ADC Free-Running ModeX
ADC Wake-Up with WCMPX
CCLConnecting LUTs in Linked Mode Requires OUTEN Set to ‘1X
D-latch is Not FunctionalX
The CCL Must be Disabled to Change the Configuration of a Single LUTX
RTCAny Write to the RTC.CTRLA Register Resets the RTC and PIT PrescalerX
Disabling the RTC Stops the PITX
TCARestart Will Reset Counter Direction in NORMAL and FRQ ModeX
TCBMinimum Event Duration Must Exceed the Selected Clock PeriodX
The TCB Interrupt Flag is Cleared When Reading CCMPHX
TCB Input Capture Frequency and Pulse-Width Measurement Mode Not Working with Prescaled ClockX
The TCA Restart Command Does Not Force a Restart of TCBX
CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM ModeX
TCDTCD Auto-Update Not WorkingX
TCD Event Output Lines May Give False EventsX
Asynchronous Input Events Not Working When TCD Counter Prescaler is UsedX
Halting TCD and Wait for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is UsedX
TWITIMEOUT Bits in the TWI.MCTRLA Register are Not AccessibleX
TWI Smart Mode Gives Extra Clock PulseX
TWI Master Mode Wrongly Detects the Start Bit as a Stop BitX
The TWI Master Enable Quick Command is Not AccessibleX
USARTTXD Pin Override Not Released When Disabling the TransmitterX
Frame Error on a Previous Message May Cause False Start Bit DetectionX
Full Range Duty Cycle Not Supported When Validating LIN Sync FieldX
Open-Drain Mode Does Not Work When TXD is Configured as OutputX
Note:
  1. This revision is the initial release of the silicon.