12.2 Timing Diagrams for Synchronous Communications

Figure 12-1. Bus Timing

SCL: Serial Clock, SDA: Serial Data I/Op

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Figure 12-2. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

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Note: The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 12-3. Data Validity
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Figure 12-4. Start and Stop Definition
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Figure 12-5. Output Acknowledge
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