12.1 DC and AC Characteristics
Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Units |
---|---|---|---|---|---|---|
VCC |
Supply Voltage |
2.7 |
3.6 |
V | ||
ICC |
Supply Current (VCC = 3.3V) |
Async Read at 3.57 MHz |
5 |
mA | ||
ICC |
Supply Current (VCC = 3.3V) |
Async Write at 3.57 MHz |
5 |
mA | ||
ICC |
Supply Current (VCC = 3.3V) |
Synch Read at 1 MHz |
5 |
mA | ||
ICC |
Supply Current (VCC = 3.3V) |
Synch Write at 1 MHz |
5 |
mA | ||
ISB |
Standby Current (VCC = 3.3V) |
VIN = VCC or GND |
100 |
μA | ||
VIL |
SDA/IO Input Low Voltage |
0 |
VCC x 0.2 |
V | ||
VIL |
CLK Input Low Voltage |
0 |
VCC x 0.2 |
V | ||
VIL |
RST Input Low Voltage |
0 |
VCC x 0.2 |
V | ||
VIH(3) |
SDA/IO Input High Voltage |
VCC x 0.7 |
5.5 |
V | ||
VIH(3) |
SCL/CLK Input High Voltage |
VCC x 0.7 |
5.5 |
V | ||
VIH(3) |
RST Input High Voltage |
VCC x 0.7 |
5.5 |
V | ||
IIL |
SDA/IO Input Low Current |
0 < VIL < VCC x 0.15 |
15 |
μA | ||
IIL |
SCL/CLK Input Low Current |
0 < VIL < VCC x 0.15 |
15 |
μA | ||
IIL |
RST Input Low Current |
0 < VIL < VCC x 0.15 |
50 |
μA | ||
IIH |
SDA/IO Input High Current |
VCC x 0.7 < VIH < VCC |
20 |
μA | ||
IIH |
SCL/CLK Input High Current |
VCC x 0.7 < VIH < VCC |
100 |
μA | ||
IIH |
RST Input High Voltage |
VCC x 0.7 < VIH < VCC |
150 |
μA | ||
VOH |
SDA/IO Output High Voltage |
20K Ω external pull-up |
VCC x 0.7 |
VCC |
V | |
VOL |
SDA/IO Output Low Voltage |
IOL = 1 mA |
0 |
VCC x 0.15 |
V | |
IOH |
SDA/IO Output High Current |
VOH |
20 |
μA | ||
IOL |
SDA/IO Output High Current |
VOL |
10 |
μA |
- Applicable over the recommended operating voltage range from VCC = 2.7V to 3.6V.
- TAC = -40°C to +85°C (unless otherwise noted).
- To prevent latch-up conditions from occurring during power-up of the AT88SCXXXXCA, VCC must be turned on before applying VIH. For powering down, VIH must be removed before turning VCC off.
Symbol |
Parameter |
Min. |
Max. |
Units |
---|---|---|---|---|
fCLK |
Async Clock Frequency |
1 |
4 |
MHz |
fCLK |
Synch Clock Frequency |
0 |
1 |
MHz |
Clock Duty cycle |
40 |
60 |
% | |
tR |
Rise Time: SDA/IO, RST |
1 |
μs | |
tF |
Fall Time: SDA/IO, RST |
1 |
μs | |
tR |
Rise Time: SCL/CLK |
9% x period |
μs | |
tF |
Fall Time: SCL/CLK |
9% x period |
μs | |
tAA |
Clock Low to Data Out Valid |
250 |
ns | |
tHD.STA |
Start Hold Time |
200 |
ns | |
tSU.STA |
Start Setup Time |
200 |
ns | |
tHD.DAT |
Data In Hold Time |
10 |
ns | |
tSU.DAT |
Data In Setup Time |
100 |
ns | |
tSU.STO |
Stop Setup Time |
200 |
ns | |
tDH |
Data Out Hold Time |
20 |
ns | |
tWR |
Write Cycle Time |
5 |
ms |
- Applicable over the recommended operating range from VCC = 2.7V to 3.6V.
- TAC = -40°C to +85°C, CL = 30pF (unless otherwise noted).