33.5.4 Control B
| Name: | CTRLB |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | NACKDIS | CCDETDIS | UPDIDIS | | | |
| Access | R | R | R | R | R | R | | | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | | | |
Bit 4 – NACKDIS Disable NACK Response
Writing this bit to
'1' disables the NACK signature sent by the UPDI if a System Reset is issued during
an ongoing LD(S) and ST(S) operation.
Bit 3 – CCDETDIS Collision and Contention Detection
Disable
If this bit is
written to '0', contention detection is enabled for 1W mode. This means that the
UPDI can detect a collision in an ongoing 1-Wire transmission.
Bit 2 – UPDIDIS UPDI
Disable
Writing a '1' to
this bit disables the UPDI PHY interface. The clock request from the UPDI is
lowered, and the UPDI is reset. All UPDI PHY configurations and KEYs will be reset
when the UPDI is disabled.
