33.5.7 ASI Control A
Name: | ASI_CTRLA |
Offset: | 0x09 |
Reset: | 0x02 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
UPDICLKSEL[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 1 | 1 |
Bits 1:0 – UPDICLKSEL[1:0] UPDI Clock Select
Writing these bits selects the UPDI clock output frequency. Default setting after reset and enable is 4MHz. Any other clock output selection is only recommended when the BOD is at the highest level. For all other BOD settings, the default 4MHz selection is recommended.
Value | Description |
---|---|
0x0 | Reserved |
0x1 | 16MHz UPDI clock |
0x2 | 8MHz UPDI clock |
0x3 | 4MHz UPDI clock (Default Setting) |