2.10 Clock Stretching

Clock stretching occurs when a client device holds the SCL line low to pause bus communication. The client may stretch the clock to allow more time to handle data or prepare a response for the host device. Clock stretching can be enabled by clearing the Clock Stretching Disable (CSD) bit of the I2CxCON1 register, and is only available in Multi-Host and Client modes.

When clock stretching is enabled, the Client Clock Stretching (CSTR) bit can be used to determine if the clock is currently being stretched, and to release the SCL line when the client is ready to continue communication. This bit cannot be set by software, but can be cleared by software after the byte has been processed.

When enabled, clock stretching is forced during buffer read/write operations. This allows the client time to either load the I2CxTXB with transmit data, or read from the I2CxRXB to clear the buffer.

In Client Receive mode, clock stretching helps prevent receive data overflows. When the first seven bits of the new byte are received into the receive Shift register while there is still data in I2CxRXB (RXBF = 1), client hardware automatically stretches the clock and sets CSTR. When the client has read the byte, the client software must clear the CSTR bit to release the clock and continue communication (see Figure 2-9).

In Client Transmit mode, clock stretching helps prevent transmit underflows. When the Transmit Buffer Empty Status (TXBE) bit is set and the I2CxCNT register is not equal to ‘0’, the client hardware stretches the clock and sets CSTR upon the eighth falling SCL edge. This allows the client software time to load the I2CxTXB with new data. Once the I2CxTXB is loaded, the client software releases the clock by clearing CSTR (see Figure 2-10).

In addition to the clock stretching features listed above, the module provides three Interrupt and Hold Enable features. When clock stretching is enabled (CSD = 0), the Interrupt and Hold Enable feature provides an interrupt and stretches the clock to allow time for address recognition, data processing, or ACK/NACK response.

The Address Interrupt and Hold Enable feature will generate and interrupt and stretch the SCL signal when an incoming address match occurs. The feature is enabled via the Address Interrupt and Hold Enable (ADRIE) bit of the I2CxPIE register. When enabled, the Client Clock Stretching (CSTR) bit and the Address Interrupt Flag (ADRIF) bit are set by hardware and the SCL line is stretched following the 8th falling SCL edge of a received matching address. Once the client has completed processing the address, the software determines whether to send an ACK or a NACK back to the host. Client software must clear both the ADRIF and CSTR bits to continue communication.

The Data Write Interrupt and Hold Enable feature provides an interrupt and stretches the SCL input after a received data byte. This feature is enabled by setting the Data Write Interrupt and Hold Enable (WRIE) bit of the I2CxPIE register. When enabled, hardware sets both the CSTR and the Data Write Interrupt Flag (WRIF) bits and stretches the SCL line after the 8th falling edge of SCL. Once completed, the client software must clear both the CSTR and WRIF bits to resume communication.

The Acknowledge Status Time Interrupt and Hold Enable feature generates an interrupt and stretches the SCL signal after the Acknowledge phase of a transmission. The feature is enabled by setting the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit. When enabled, the module hardware sets both the CSTR and Acknowledge Status Time Interrupt Flag (ACKTIF) bit and stretches the clock after the 9th falling edge of SCL. This feature enables clock stretching for all address, read, or write transactions. Once completed, client software must clear both the CSTR and ACKTIF bits to continue communication.