2.1 Dedicated Transmit/Receive Buffers

The I²C module has two dedicated data buffers, one for transmission (I2CxTXB) and one for reception (I2CxRXB) (see Figure 2-1).

The transmit buffer, I2CxTXB, is loaded from the software or from the Direct Memory Access (DMA) module (see Figure 2-2). When transmission begins, data loaded into the I2CxTXB is shifted into the transmit Shift register and out onto the bus. The I2CxTXB can be loaded when the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), indicating that the buffer is empty. When the buffer is empty and the I2CxCNT register is not equal to ‘0’, the I2C Transmit Interrupt Flag (I2CxTXIF) bit is set, and the generic I2C Interrupt Flag (I2CxIF) will also be set if the I2C Transmit Interrupt Enable (I2CxTXIE) bit is set. Loading a new byte of data into the I2CxTXB clears the I2CxTXIF flag bit. If user software attempts to load the I2CxTXB while it is full, the Transmit Write Error Status (TXWE) bit is set, a NACK is generated, and the new data are ignored. If the TXWE bit is set, the software must clear this bit before attempting to load the buffer again.

The receive buffer, I2CxRXB, holds one byte of data that is shifted in from the receive Shift register. User software or the DMA can read the byte through the I2CxRXB register (see Figure 2-2). When a new byte is received, the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit are set, and the generic I2CxIF will also be set if the I2C Receive Interrupt Enable (I2CxRXIE) bit is set. Reading I2CxRXB clears both RXBF and I2CxRXIF. If the buffer is read while empty (RXBF = 0), the Receive Read Error Status (RXRE) bit is set, and the module generates a NACK. User software must clear the RXRE bit to resume normal operation.

Both transmit and receive buffers can be cleared by setting the Clear Buffer (CLRBF) bit of the I2CxSTAT1 register, which also clears both the I2CxTXIF and I2CxRXIF Interrupt Flags.