2.2 Address Buffers and Registers
The I2C module has two Address Buffer registers, I2CxADB0 and I2CxADB1, that can be used as receive buffers in Client mode (see Table 2-2). This differs from the MSSP module in that the MSSP module only used the SSPBUF to receive or transmit an address (or data). The address buffers are enabled via the Address Buffer Disable (ABD) bit. When ABD is cleared, the address buffers are enabled; when the ABD is set, the address buffers are disabled.
When the ABD bit is cleared and in 7-bit Addressing mode, I2CxADB0 is loaded with the matching received client address and the R/W bit, and I2CxADB1 is unused. In 10-bit Addressing mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, and I2CxADB1 is loaded with the upper eight bits of the matching address, including the R/W bit.
When the ABD bit is set and in 7-bit Addressing mode, I2CxRXB is loaded with the matching received client address and R/W bit, and neither I2CxADB0/1 are used. In 10-bit Addressing mode, I2CxRXB is loaded with both the high and low matching address bytes. In this case, user software must read I2CxRXB before the receive Shift register will load I2CxRXB with the matching lower address byte. I2CxADB0/1 are also unused in 10-bit Addressing mode.
Modes | MODE[2:0] | I2CADB0 | I2CADB1 |
---|---|---|---|
Client (7-bit) | 000 | RX | Unused |
001 | |||
Client (10-bit) | 010 | RX | RX |
011 |
The I2C module has four additional Client mode Address registers, I2CxADR0/1/2/3. These registers can hold up to four 7-bit client addresses or up to two 10-bit client addresses. The I2CxADR0/1/2/3 registers can also be used to form mask registers (see Table 2-2).
Modes | MODE[2:0] | I2CADR0 | I2CADR1 | I2CADR2 | I2CADR3 |
---|---|---|---|---|---|
7-bit | 000 | 7-bit address | 7-bit address | 7-bit address | 7-bit address |
7-bit w/masking | 001 | 7-bit address | 7-bit mask for I2CxADR0 | 7-bit address | 7-bit mask for I2CxADR2 |
10-bit | 010 | Lower address byte | Upper address byte | Lower address byte | Upper address byte |
10-bit w/masking | 011 | Lower address byte | Upper address byte | Lower address mask | Upper address mask |
In 10-bit Addressing mode, I2CxADR0 and I2CxADR1 are combined to hold the 10-bit client
address, while I2CxADR2 and I2CxADR3 are combined to hold a second 10-bit client
address. I2CxADR0 and I2CxADR2 hold the lower eight bits of the 10-bit addresses, while
I2CxADR1 and I2CxADR3 hold the upper two bits of the 10-bit addresses, with the
R/W bits and the five digit ‘11110
’ code
assigned to the five Most Significant bits of the address high bytes. If address masking
is desired, I2CxADR0 and I2CxADR1 are combined to form the 10-bit client address, while
I2CxADR2 and I2CxADR3 are combined to form the 10-bit address mask. Address masking may
be used to ignore the five-bit address code loaded into the Most Significant bits of the
upper address byte.
11110
’ code is specified by the I2C Specification, but
is not strictly enforced by Microchip. The user must ensure that the correct bit values
are loaded into the 10-bit high address byte. If a host device has included that
specific code in the address it intends to transmit, the client must also include those
bits in the client address.