37.4 ADC Operation

The High-Speed Successive Approximation Register (SAR) ADC is designed to support power conversion and motor control applications and consists of two individual ADC cores. The dedicated ADC core has a single analog input (after alternate selection) connected to its S&H circuit. Since this ADC core samples a dedicated analog input, it is termed a “dedicated” ADC core. A dedicated ADC core is used to measure or capture time-sensitive or transitory analog signals. The shared ADC core has multiple analog input connected to its S&H circuit through a multiplexer. However, this ADC core is capable of up to 1 Msps sample rate.

The analog inputs connected to the ADC cores are Class 1, Class 2 and Class 3 inputs. The number of inputs designated for each class depends on the specific device. For the PIC32CX-BZ6, the following arrangement is provided.

Class 1 = AN0
Class 2 = AN1 to AN7
Class 3 = AN8 to AN18

Note: These four channels are reserved internal nodes.

BG_VREF is AN19
CP_1V2 is AN20
VDD_1V2 is AN21
VDD33/2 is AN22

The property of each class of analog input is described in the following table.

Table 37-1. Analog Input Class
ADC Cores	Analog Input Class	Trigger	Trigger Action
Dedicated ADC core	Class 1	Individual trigger source or scan trigger	Ends sampling and starts conversion
Shared ADC core	Class 2	Individual trigger source or scan trigger	Starts sampling sequence or begins scan sequence
Shared ADC core with input scan	Class 3	Scan trigger	Starts scan sequence

Class 1 analog input properties:

Class 1 inputs are associated with a dedicated ADC core. Dedicated ADC has a single Class 1 input associated with it at a given time. The (alternate) input selection is made through the SH0ALT bits in the ADCTRGMODE register. Regardless of the alternate input selection, the trigger source and the result register remains the same.

Class 1 input has a unique trigger (selected by the ADCTRGx register) and upon arrival of the trigger, ends sampling and starts conversion. Upon completion of conversion, the ADC core reverts back to sampling mode. When a Class 1 input is enabled and is not being converted, it is always sampled.

Class 1 inputs can be part of a scan list, triggered by the common scan trigger source.

Figure 37-2. Sample and Conversion Sequence for Dedicated ADC Cores

Class 2 and Class 3 analog input properties:

Class 2 inputs are used on the shared ADC core, either individually triggered or as part of a scan list. In case of using individually, their unique trigger selected by the ADCTRGx register triggers the Class 2 inputs.
The analog inputs on the shared ADC have a natural order of priority (for example, AN6 has a higher priority than AN7).
Class 3 inputs are used exclusively for scanning and share a common trigger source (scan trigger).
Class 3 analog inputs share both the ADC core and the trigger source; therefore, the only method possible to convert them is to scan them sequentially for each incoming scan trigger event, where scanning occurs in the natural order of priority.
The arrival of a trigger in the shared ADC core only starts the sampling. When the trigger arrives, the ADC core goes into the Sampling mode for the sampling time decided by the SAMC[9:0] bits (ADCCON2[25:16]). At the end of sampling, the ADC starts conversion. Upon completion of conversion, the ADC core is used to convert the next in line Class 2 or Class 3 inputs according to the natural order of priority. When a shared analog input (Class 2 or Class 3) has completed all conversion and no trigger is pending, the ADC core is disconnected from all analog inputs.
Figure 37-3. Sample and Conversion Sequence for Shared ADC Cores