37.11 ADC Sampling Requirements

The analog input model of the 12-bit ADC is illustrated in the following figure. The total acquisition time for the analog-to-digital conversion is a function of the internal circuit settling time and the holding capacitor charge time.

For the ADC core to meet its specified accuracy, the charge holding capacitor (C_Samp) must be allowed to fully charge to the voltage level on the analog input pin. The analog output source impedance (R_SRC), the interconnect impedance (R_IC) and the internal sampling switch (R_{IN_ADC}) impedance combine to directly affect the time required to charge the C_Samp. The combined impedance of the analog sources must, therefore, be small enough to fully charge (to within one-fourth LSB of the desired voltage) the holding capacitor within the selected sample time. The internal holding capacitor is in the discharged state prior to each sample operation.

One T_AD7 time period must be allowed between conversions for the acquisition time. See Electrical Characteristics from Related Links.

Equation 37-3. Sampling time (T_SAMP)

T_{S A M P} = (C_{S A M P} + C_{int}) \times (R_{S R C} + R_{P C B} + R_{P A D} + R_{I C} + R_{(I N_A D C)}) \times \ln (2^{(N + 2)})

Figure 37-12. 12-bit ADC Analog Input Model

Note: The C_PIN value depends on the device package and is not tested. The effect of the C_PIN is negligible if R_SRC 5 k.

Legend:

C_PIN = 4pF (Input capacitance)
R_{IN_ADC} = 200Ω (Sampling switch resistance)
R_SRC = Source resistance
I_LEAKAGE = Leakage current at the pin due to various junctions
V_T = Threshold voltage
R_IC = 60Ω for dedicated ADC and 45Ω for shared ADC
C_Samp = 5 pF (Sample/hold capacitance)
R_PAD = 510Ω, including ESD + Switch resistance
C_int = 0 pF for dedicated and 9.2 pF for shared ADC (sum of switches connected to internal net and the routing capacitance)