17.5.7 Register Access Protection

Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1)

Note:

Optional write protection is indicated by the PAC Write Protection property in the register description.
If halting the CPU in the Debug mode, all write protection is automatically disabled. Write protection does not apply for accesses through an external debugger.

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