Table 49-1. Timer Counter Clock AssignmentName | Definition |
---|
TIMER_CLOCK1 | PCK6 or PCK7 (TC0 only) |
TIMER_CLOCK2 | MAIN_CLK/8 |
TIMER_CLOCK3 | MAIN_CLK/32 |
TIMER_CLOCK4 | MAIN_CLK/128 |
TIMER_CLOCK5 (1)
| SLOW_CLK |
- When SLOW_CLK is
selected for Peripheral Clock (CSS = 0 in PMC Host Clock register), SLOW_CLK input is equivalent to Peripheral Clock.
- The PCK6 or PCK7 (TC0 only)
frequency must be at least three times lower than peripheral clock frequency.
Figure 49-1. Timer Counter Module N Block Diagram (N = 0,1,2,3)Note: The QDEC connections are detailed in
"Predefined Connection of the Quadrature Decoder with Timer Counters".
Table 49-2. Channel Signal DescriptionSignal Name | Description |
---|
XC0, XC1, XC2 | External Clock Inputs |
TIOAx | Capture Mode: Timer Counter
Input
Waveform Mode: Timer Counter Output |
TIOBx | Capture Mode: Timer Counter
Input
Waveform Mode: Timer Counter Input/Output |
INT | Interrupt Signal Output (internal
signal) |
SYNC | Synchronization Input Signal (from
configuration register) |