34.4.4.1 Single Block Transfer With Single Microblock

  1. Read the XDMAC Global Channel Status Register (XDMAC_GS) to select a free channel.
  2. Clear the pending Interrupt Status bits by reading the selected XDMAC Channel x Interrupt Status Register (XDMAC_CISx).
  3. Write the XDMAC Channel x Source Address Register (XDMAC_CSAx) for channel x.
  4. Write the XDMAC Channel x Destination Address Register (XDMAC_CDAx) for channel x.
  5. Program field UBLEN in the XDMAC Channel x Microblock Control Register (XDMAC_CUBCx) with the number of data.
  6. Program the XDMAC Channel x Configuration Register (XDMAC_CCx):
    1. Clear XDMAC_CCx.TYPE for a memory-to-memory transfer, otherwise set this bit.
    2. Configure XDMAC_CCx.MBSIZE to the memory burst size used.
    3. Configure XDMAC_CCx.SAM and DAM to Memory Addressing mode.
    4. Configure XDMAC_CCx.DSYNC to select the peripheral transfer direction.
    5. Configure XDMAC_CCx.CSIZE to configure the channel chunk size (only relevant for peripheral synchronized transfer).
    6. Configure XDMAC_CCx.DWIDTH to configure the transfer data width.
    7. Configure XDMAC_CCx.SIF, XDMAC_CCx.DIF to configure the Host interface used to read data and write data, respectively.
    8. Configure XDMAC_CCx.PERID to select the active hardware request line (only relevant for a peripheral synchronized transfer).
    9. Set XDMAC_CCx.SWREQ to use a software request (only relevant for a peripheral synchronized transfer).
  7. Clear the following registers:
    1. The XDMAC Channel x Next Descriptor Control Register (XDMAC_CNDCx).
    2. The XDMAC Channel x Block Control Register (XDMAC_CBCx).
    3. The XDMAC Channel x Data Stride Memory Set Pattern Register (XDMAC_CDS_MSPx).
    4. The XDMAC Channel x Source Microblock Stride Register (XDMAC_CSUSx).
    5. The XDMAC Channel x Destination Microblock Stride Register (XDMAC_CDUSx).
  8. Enable the Microblock interrupt by writing a ‘1’ to the BIE bit in the XDMAC Channel x Interrupt Enable Register (XDMAC_CIEx). Enable the Channel x Interrupt Enable bit by writing a ‘1’ to the IEx bit in the XDMAC Global Interrupt Enable Register (XDMAC_GIE).
  9. Enable channel x by writing a ‘1’ to the ENx bit in the XDMAC Global Channel Enable Register (XDMAC_GE). XDMAC_GS.STx (the XDMAC Channel x Status bit) is set by hardware.
  10. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the Channel Status bit.