8.2 Power-Down Considerations

If VDDCORE, VDDPLL, and VDDUTMIC are not supplied by the embedded voltage regulator, VDDIO, VDDIN, VDDPLLUSB, and VDDUTMII should fall simultaneously prior to VDDCORE, VDDPLL and VDDUTMIC falling. The VDDCORE falling slope must not be faster than 20 V/ms.

To prevent any overcurrent at power-down, it is required that VREFP falls simultaneously with VDDIO and VDDIN.

Time delay between VDD = 1V (t1) and VDD1 = 0.8V (t2) = 100 us minimum.