13.2 Nested Vector Interrupt Controller

The Nested Vector Interrupt Controller (NVIC) in the PIC32CZ CA70/MC70 devices supports up to 74 interrupt lines with 8 different priority levels + 1 Non-Maskable Interrupt (NMI) line.

For additional information, refer to the "Cortex-M7 Technical Reference Manual" which is avaialbe for download at www.arm.com.

Each interrupt line is connected to one peripheral instance, as shown in the following table. Each peripheral can have one or more interrupt flags, located in the peripheral’s Status Register (SR).

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a ‘1’ to the corresponding bit in the peripheral’s Interrupt Enable Register (IER) and disabled by writing a ‘1’ to the corresponding bit in the peripheral’s Interrupt Disable Register (IDR).

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in the ISPR/ICPR registers).

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in the ISER/ICER registers). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

For additional infromation on peripheral interrupts and associated NVIC lines, refer to the Peripherals section and the respective Interrupt Enable Register (IER).