7.6.1 VREGCON
Note:
- System and peripheral inputs should not exceed 500 kHz in ULP mode.
Voltage Regulator Control Register
| Name: | VREGCON |
| Address: | 0xEDA |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PMSYS[1:0] | VREGPM[1:0] | ||||||||
| Access | RO | RO | R/W | R/W | |||||
| Reset | g | g | 1 | 0 | |||||
Bits 5:4 – PMSYS[1:0] System Power Mode Status bits
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | ULP regulator is active |
| 01 | Main regulator in LP mode is active |
| 00 | Main regulator in HP mode is active |
Bits 1:0 – VREGPM[1:0] Voltage Regulator Power Mode Selection bit
| Value | Description |
|---|---|
| 11 | Reserved. Do not use. |
| 10 | ULP regulator(1) |
| 01 | Main regulator in LP mode |
| 00 | Main regulator in HP mode |