7.6.2 CPUDOZE

Doze and Idle Register
Note:
  1. When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
Name: CPUDOZE
Address: 0xED2

Bit 76543210 
 IDLENDOZENROIDOE DOZE[2:0] 
Access R/WR/W/HC/HSR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – IDLEN Idle Enable bit

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1

A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)

0

A SLEEP instruction places the device into full Sleep mode

Bit 6 – DOZEN

Doze Enable bit(1)
ValueDescription
1

The CPU executes instruction cycles according to DOZE setting

0

The CPU executes all instruction cycles (fastest, highest power operation)

Bit 5 – ROI Recover-On-Interrupt bit

ValueDescription
1

Entering the Interrupt Service Routine (ISR) makes DOZEN = 0, bringing the CPU to full-speed operation

0

Interrupt entry does not change DOZEN

Bit 4 – DOE Doze-On-Exit bit

ValueDescription
1

Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation

0

RETFIE does not change DOZEN

Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

ValueDescription
111

1:256

110

1:128

101

1:64

100

1:32

011

1:16

010

1:8

001

1:4

000

1:2

When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.