4.7.2 CONFIG2

Supervisor

Name: CONFIG2
Address: 0x300002

Configuration Word 2

Bit 15141312111098 
 XINST DEBUGSTVRENPPS1WAYZCDBORV[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 1111111 
Bit 76543210 
 BOREN[1:0]LPBOREN   PWRTEMCLRE 
Access R/WR/WR/WR/WR/W 
Reset 01111 

Bit 15 – XINST Extended Instruction Set Enable bit

ValueDescription
1Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0Extended Instruction Set and Indexed Addressing mode enabled

Bit 13 – DEBUG Debugger Enable bit

ValueDescription
1Background debugger disabled
0Background debugger enabled

Bit 12 – STVREN Stack Overflow/Underflow Reset Enable bit

ValueDescription
1Stack Overflow or Underflow will cause a Reset
0Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAY PPSLOCKED bit One-Way Set Enable bit

ValueDescription
1The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented
0The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is executed)

Bit 10 – ZCD ZCD Disable bit

ValueDescription
1ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0ZCD always enabled, PMDx[ZCDMD] bit is ignored

Bits 9:8 – BORV[1:0] Brown-out Reset Voltage Selection bit

ValueDescription
11Brown-out Reset Voltage (VBOR) set to 1.90V
10Brown-out Reset Voltage (VBOR) set to 2.45V
01Brown-out Reset Voltage (VBOR) set to 2.7V
00Brown-out Reset Voltage (VBOR) set to 2.85V

Bits 7:6 – BOREN[1:0] Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit

ValueDescription
11Brown-out Reset enabled, SBOREN bit is ignored
10Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
01Brown-out Reset enabled according to SBOREN
00Brown-out Reset disabled

Bit 5 – LPBOREN Low-Power BOR Enable bit

ValueDescription
1Low-Power Brown-out Reset is disabled
0Low-Power Brown-out Reset is enabled

Bit 1 – PWRTE Power-up Timer Enable bit

ValueDescription
1PWRT disabled
0PWRT enabled

Bit 0 – MCLRE Master Clear (MCLR) Enable bit

ValueNameDescription
xIf LVP = 1RE3 pin function is MCLR
1If LVP = 0MCLR pin is MCLR
0If LVP = 0MCLR pin function is port defined function