20.7.2 Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections.

Table 20-4. Timer Gate Sources
GSS Gate Source
Timer1 Timer3 Timer5
11000-11111 Reserved Reserved Reserved
10111 CLC8_out CLC8_out CLC8_out
10110 CLC7_out CLC7_out CLC7_out
10101 CLC6_out CLC6_out CLC6_out
10100 CLC5_out CLC5_out CLC5_out
10011 CLC4_out CLC4_out CLC4_out
10010 CLC3_out CLC3_out CLC3_out
10001 CLC2_out CLC2_out CLC2_out
10000 CLC1_out CLC1_out CLC1_out
01111 Reserved Reserved Reserved
01110 ZCDOUT ZCDOUT ZCDOUT
01101 CMP2OUT CMP2OUT CMP2OUT
01100 CMP1OUT CMP1OUT CMP1OUT
01011 PWM4OUT PWM4OUT PWM4OUT
01010 PWM3OUT PWM3OUT PWM3OUT
01001 CCP2OUT CCP2OUT CCP2OUT
01000 CCP1OUT CCP1OUT CCP1OUT
00111 TMR6OUT (post-scaled) TMR6OUT (post-scaled) TMR6OUT (post-scaled)
00110 TMR5 overflow TMR5 overflow Reserved
00101 TMR4OUT (post-scaled) TMR4OUT (post-scaled) TMR4OUT (post-scaled)
00100 TMR3 overflow Reserved TMR3 overflow
00011 TMR2OUT (post-scaled) TMR2OUT (post-scaled) TMR2OUT (post-scaled)
00010 Reserved TMR1 overflow TMR1 overflow
00001 TMR0 overflow TMR0 overflow TMR0 overflow
00000 Pin selected by T1GPPS Pin selected by T3GPPS Pin selected by T5GPPS

Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section.