20.7.2 Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections.

Table 20-4. Timer Gate Sources
GSSGate Source
Timer1Timer3Timer5
11000-11111ReservedReservedReserved
10111CLC8_outCLC8_outCLC8_out
10110CLC7_outCLC7_outCLC7_out
10101CLC6_outCLC6_outCLC6_out
10100CLC5_outCLC5_outCLC5_out
10011CLC4_outCLC4_outCLC4_out
10010CLC3_outCLC3_outCLC3_out
10001CLC2_outCLC2_outCLC2_out
10000CLC1_outCLC1_outCLC1_out
01111ReservedReservedReserved
01110ZCDOUTZCDOUTZCDOUT
01101CMP2OUTCMP2OUTCMP2OUT
01100CMP1OUTCMP1OUTCMP1OUT
01011PWM4OUTPWM4OUTPWM4OUT
01010PWM3OUTPWM3OUTPWM3OUT
01001CCP2OUTCCP2OUTCCP2OUT
01000CCP1OUTCCP1OUTCCP1OUT
00111TMR6OUT (post-scaled)TMR6OUT (post-scaled)TMR6OUT (post-scaled)
00110TMR5 overflowTMR5 overflowReserved
00101TMR4OUT (post-scaled)TMR4OUT (post-scaled)TMR4OUT (post-scaled)
00100TMR3 overflowReservedTMR3 overflow
00011TMR2OUT (post-scaled)TMR2OUT (post-scaled)TMR2OUT (post-scaled)
00010ReservedTMR1 overflowTMR1 overflow
00001TMR0 overflowTMR0 overflowTMR0 overflow
00000Pin selected by T1GPPSPin selected by T3GPPSPin selected by T5GPPS

Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section.