20.14.3 TMRxCLK
| Name: | TMRxCLK |
| Address: | 0xFD1,0xFCB,0xFC5 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CS[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 4:0 – CS[4:0] Timer Clock Source Selection bits
Refer to the clock source selection table.
| Reset States: |
|
| Name: | TMRxCLK |
| Address: | 0xFD1,0xFCB,0xFC5 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CS[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Refer to the clock source selection table.
| Reset States: |
|
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