14.12.4 CRCACC
| Name: | CRCACC |
| Address: | 0xF71 |
| Reset: | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCACCH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCACCL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – CRCACCH[7:0] CRC Accumulator Register most significant byte
Writing to this register writes the Most Significant Byte of the CRC accumulator register. Reading from
this register reads the Most Significant Byte of the CRC accumulator.
Bits 7:0 – CRCACCL[7:0] CRC Accumulator Register least significant byte
Writing to this register writes the Least Significant Byte of the CRC accumulator register. Reading from
this register reads the Least Significant Byte of the CRC accumulator.