7.2.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

  1. External Reset input on MCLR pin, if enabled
  2. BOR Reset, if enabled
  3. Low-Power Brown-Out Reset (LPBOR), if enabled
  4. POR Reset
  5. Windowed Watchdog Timer, if enabled
  6. All interrupt sources except clock switch interrupt can wake-up the part.

The first five events will cause a device Reset. The last one event is considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to the "Determining the Cause of a Reset" section.

When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake-up through an interrupt event, the corresponding Interrupt Enable bit must be enabled, as well as the Peripheral Interrupt Enable bit (PEIE = 1), for every interrupt not in PIR0. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up.

Upon a wake from a Sleep event, the core will wait for a combination of three conditions before beginning execution. The conditions are:

  • PFM Ready
  • COSC-Selected Oscillator Ready
  • BOR Ready (unless BOR is disabled)