3.2.2.1 Connectors
PL360MB board includes following connectors:
- Mains connector, J1.
Table 3-1. Mains Connector, J1 Pin Signal Name Description 1 L Line 2 N Neutral - Dual triple row non-isolated UARTs
connector, J5.
Table 3-2. UARTs Connector, J5 Pin Signal Name Description 1 UTXD0 Serial data output signal of UART0 2 URXD0 Serial data input signal of UART0 3 GND Ground 4 UTXD1 Serial data output signal of UART1 5 UTXD1 Serial data input signal of UART1 6 GND Ground - Micro-B USB connector for the
isolated UART0, J9.
Table 3-3. USB Device Connector, J9 Pin Signal Name Description 1 VBUS 5V power 2 D+ Data Plus 3 D- Data Minus 4 ID On the Go Identification 5 GND Ground - Xplained PRO extension connector,
J10.
Table 3-4. Xplained PRO Connector, J10 Pin Mnemonic 1 ID 2 GND 3 ADC 4 ADC 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 IRQ 10 GPIO 11 TWD 12 TWCK 13 RXD 14 TXD 15 CS 16 MOSI 17 MISO 18 SCK 19 GND 20 GND - BNC connector for PLC signal,
J11.
Table 3-5. BNC Connector, J11 Pin Signal Name Description 1 PLC+ PLC Signal + 2 PLC- PLC Signal - - JTAG/SWD 20-pin IDC connector for
SAM4CMS16C, J13.
Table 3-6. JTAG/ICE Connector, J13 Pin Mnemonic Description 1 Vcc (3.3V power) This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. 2 Vcc (opt) (3.3V power) This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. 3 TRST (TARGET RESET) JTAG Reset (active-low output signal that resets the target). Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. 4 GND Ground. 5 TDI (TEST DATA INPUT) JTAG data input of target CPU (serial data output line, sampled on the rising edge of the TCK signal). It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. 6 GND Ground. 7 TMS (TEST MODE SELECT) JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. 8 GND Ground. 9 TCK (TEST CLOCK) JTAG clock signal to target CPU (output timing signal, for synchronizing test logic and control register access). It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. 10 GND Ground. 11 RTCK Input Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. 12 GND Ground. 13 TDO (JTAG TEST DATA OUTPUT) JTAG data output from target CPU (serial data input from the target). Typically connected to TDO on target CPU. 14 GND Ground. 15 RESET Active-low reset signal. Target CPU reset signal. 16 GND Ground. 17 RFU This pin is not connected in SAM-ICE. 18 GND Ground. 19 RFU This pin is not connected in SAM-ICE. 20 GND Ground. - VDD Output connector,
J15.
Table 3-7. VDD Output Connector, J15 Pin Signal Name Description 1 VDD VDD voltage 2 GND Ground 3 - - - PL360 SWD 10-pin connector for PL360
(for internal use only), J18.
Table 3-8. SW-DP Connector, J18 Pin Mnemonic Description 1 VCC This is the target reference voltage. 2 SWDIO/TMS Serial Wire Input / Output. 3 GND Ground. 4 SWDCLK/TCK Serial Wire Clock. 5 GND Ground. 6 SWO/TDO Trace Asynchronous Data Out from target CPU (serial data input from the target). 7 KEY - 8 NC/TDI Test Data Input. This pin is not connected. 9 GND Detect Ground. 10 nRESET Target CPU reset signal. - Input Current Sensor connector, J3
& J19.
Table 3-9. Input Current Sensor Connector, J3 Pin Description 1 Differential input current sensor. 2 Differential input current sensor. Table 3-10. Input Current Sensor Connector, J19 Pin Description 1 Differential input current sensor. 2 Differential input current sensor. - PWM Isolated Energy Indication
connector, J24 & J25.
Table 3-11. PWM Isolated Wh Connector, J24 Pin Signal Name Description 1 CF1+ Wh pulse. 2 CF1- Wh pulse. Table 3-12. PWM Isolated VArh Connector, J25 Pin Signal Name Description 1 CF2+ VArh pulse. 2 CF2- VArh pulse. - Relay Control Port connector,
J26.
Table 3-13. Relay Control Port Connector, J26 Pin Mnemonic 1 PA26 2 PA19 3 PA18 4 GND