11.6.2 Design Layout Recommendations
When designing the ISI interface, consider the following recommendations:
- Match signal lengths to within 20 mils. Affected PIOs in the example above are PC0 to PC7 and PC12 to PC15.
- Place the clock lines (PC12 and PC15) at least three times the trace width away from other signals for noise immunity.
- Place data signals at least two times the trace width away from any other data traces.
- Place data signals at least two times the trace width away from any copper plane.