8.1.5.2.6 Boot Process

The device always boots at address 0x0 from the ROM. Depending on the GPNVM bits [8:5], the ROM code instructs the Core 0 to execute code in Flash either by a non-secure boot process (SAM-BA Monitor or Standard Boot) or by a secure boot process (Secure SAM-BA Monitor or Secure Boot).

After power-up or full system reset, the second peripheral set is maintained in reset and with no clock.

The second peripheral set consists of the following peripherals: MEM2MEM1 (ID78), TC3(ID79 to 84) , PIOD (ID85/86), UART (ID87), MCSPI (ID89), PWM (ID90) and are clocked by the Main System Bus Clocks MCK1, MCK1DIV and the reset line managed by CPEREN bit (second peripheral set enable in RSTC.MR).