2.9.2 Functional Description
Figure 2-49 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j, that allow frequency scaling of the clock signal:
- The i divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64, and the resultant frequency is available at the output of the PLL block.
- The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock is available at CLK1.
- The two dividers together can implement any combination of multiplication and division up to a maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50 duty cycle.
- The output frequencies of the two clocks are given by the following formulas (fREF is the reference clock frequency):fCLK1 = fREF × (DividerI) / (DividerJ)fCLK2 = fREF × (DividerI)
- CLK2 provides the PLL output directly—without division
The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These functions and their possible values are detailed in the following table.
The delay lines shown in Figure 2-49 are programmable. The feedback clock path can be delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in increments of 250 ps. The following table describes the usage of these bits. The delay increments are independent of frequency, so this results in phase changes that vary with frequency. The delay value is highly dependent on VCC and the speed grade.
The following figure is a logical diagram of the various control signals to the PLL and shows how the PLL interfaces with the global and routing networks of the FPGA. Note that not all signals are user-accessible. These non-user-accessible signals are used by the place-and-route tool to control the configuration of the PLL. The user gains access to these control signals either based upon the connections built in the user's design or through the special macros (see Table 2-88) inserted into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal.
| Signal Name | Type | User Accessible | Allowable Values | Function |
|---|---|---|---|---|
| RefCLK | Input | Yes | — | Reference Clock for the PLL |
| FB | Input | Yes | — | Feedback port for the PLL |
| PowerDown | Input | Yes | — | PLL power down control |
| 0 | PLL powered down | |||
| 1 | PLL active | |||
| DIVI[5:0] | Input | Yes | 1 to 64, in unsigned binary notation offset by -1 | Sets value for feedback divider (multiplier) |
| DIVJ[5:0] | Input | Yes | Sets value for CLK1 divider | |
| LowFreq | Input | Yes | — | Input frequency range selector |
| 0 | 50–200 MHz | |||
| 1 | 14–50 MHz | |||
| Osc[2:0] | Input | Yes | — | Output frequency range selector |
| XX0 | 400–1000 MHZ | |||
| 001 | 200–400 MHZ | |||
| 011 | 100–200 MHZ | |||
| 101 | 50–100 MHZ | |||
| 111 | 20–50 MHZ | |||
| DelayLine[4:0] | Input | Yes | –15 to +15 (increments), in signed-and-magnitude binary representation | Clock Delay (positive/negative) in increments of 250 ps, with maximum value of ± 3.75 ns |
| FBMuxSel | Input | No | — | Selects the source for the feedback input |
| REFSEL | Input | No | — | Selects the source for the reference clock |
| OUTSEL | Input | No | — | Selects the source for the routed net output |
| PLLSEL | Input | No | — | ROOTSEL and PLLSEL are used to select the source of the global clock network |
| ROOTSEL | Input | No | — | — |
| Lock | Output | Yes | — | High value indicates PLL has locked |
| CLK1 | Output | Yes | — | PLL clock output |
| CLK2 | Output | Yes | — | PLL clock output |