2.9.1 Physical Implementation

The eight PLL blocks are arranged in two groups of four. One group is located in the center of the northern edge of the chip, while the second group is centered on the southern edge. The northern group is associated with the four HCLK networks (for example, PLLA can drive HCLKA), while the southern group is associated with the four CLK networks (for example, PLLE can drive CLKE).

Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core. The following figure illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply through a 250Ω resistor. Furthermore, 0.1 μF and 10 μF decoupling capacitors should be connected across the VCCPLL and VCOMPPLL pins.

The VCOMPPLL pin should never be grounded (see Figure 2-2).

The I/O pads associated with the PLL can also be configured for regular I/O functions, except when it is used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair, single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair with [H]CLKxP.

The block marked “/i Delay Match” is a fixed delay equal to that of the i divider. The “/j Delay Match” block has the same function as its j divider counterpart.