2.9.4 Special PLL Macros
The following tables show the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing resources.
| Macro Name | Usage |
|---|---|
| PLLINT | Connects RefCLK to a regular routed net or a pad. |
| PLLRCLK | Connects CLK1 or CLK2 to the CLK network. |
| PLLHCLK | Connects CLK1 or CLK2 to the HCLK network. |
| PLLOUT | Connects CLK1 or CLK2 to a regular routed net. |
| Parameter | Value | Notes |
|---|---|---|
| Frequency Ranges | ||
| Reference frequency (min.) | 14 MHz | Lowest input frequency |
| Reference frequency (max.) | 200 MHz | Highest input frequency |
| OSC frequency (min.) | 20 MHz | Lowest output frequency |
| OSC frequency (max.) | 1 GHz | Highest output frequency |
| Jitter | ||
| Long-term jitter (max.) | 1% | Percentage of period, low reference clock frequencies |
| Long-term jitter (max.) | 100ps | High reference clock frequencies |
| Short-term jitter (max.) | 50ps+1% | Percentage of output frequency |
| Acquisition Time (lock) from Cold Start | ||
| Acquisition time (max.)1 | 400 cycles | Period of low reference clock frequencies |
| Acquisition time (max.)1 | 1.5 μs | High reference clock frequencies |
| Power Consumption | ||
| Analog supply current (low freq.) | 200 μA | Current at minimum oscillator frequency |
| Analog supply current (high freq.) | 200 μA | Frequency-dependent current |
| Digital Supply Current (low freq.) | 0.5 μA/MHz | Current at maximum oscillator frequency, unloaded |
| Digital supply current (high freq.) | 1 μA/MHz | Frequency-dependent current |
| Duty Cycle | ||
| Minimum output duty cycle | 45% | — |
| Maximum output duty cycle | 55% | — |
Note:
- The lock bit remains Low until RefCLK reaches the minimum input frequency.