2.5.3.1 Timing Characteristics

The following table lists the timing characteristics of LVPECL.

Table 2-65. LVPECL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
LVPECL Output Module Timing
t_DP	Input buffer	—	1.66	—	1.89	—	2.22	ns
t_PY	Output buffer	—	2.24	—	2.55	—	3.00	ns
t_ICLKQ	Clock-to-Q for the I/O input register	—	0.67	—	0.77	—	0.90	ns
t_OCLKQ	Clock-to-Q for the I/O output register and the I/O enable register	—	0.67	—	0.77	—	0.90	ns
t_{_SUD}	Data input set-up	—	0.23	—	0.27	—	0.31	ns
t_SUE	Enable input set-up	—	0.26	—	0.30	—	0.35	ns
t_HD	Data input hold	—	0.00	—	0.00	—	0.00	ns
t_HE	Enable input hold	—	0.00	—	0.00	—	0.00	ns
t_CPWHL	Clock pulse width high to low	0.39	—	0.39	—	0.39	—	ns
t_CPWLH	Clock pulse width low to high	0.39	—	0.39	—	0.39	—	ns
t_WASYN	Asynchronous pulse width	0.37	—	0.37	—	0.37	—	ns
t_REASYN	Asynchronous recovery time	—	0.13	—	0.15	—	0.17	ns
t_HASYN	Asynchronous removal time	—	0.00	—	0.00	—	0.00	ns
t_CLR	Asynchronous Clear-to-Q	—	0.23	—	0.27	—	0.31	ns
t_PRESET	Asynchronous Preset-to-Q	—	0.23	—	0.27	—	0.31	ns