2.3.5 I/O Standard Electrical Specifications  

The following tables show the I/O standard electrical specifications.

Table 2-23. Input Capacitance
SymbolParameterConditionsMin.Max.Units
CINInput capacitanceVIN = 0, f = 1.0 MHz—10pF
CINCLKInput capacitance on HCLK and RCLK pinVIN = 0, f = 1.0 MHz—10pF
Table 2-24.  I/O Input Rise Time and Fall Time1
Input BufferInput Rise/Fall Time (min.)Input Rise/Fall Time (max.)
LVTTLNo requirement50 ns
LVCMOS 2.5VNo requirement50 ns
LVCMOS 1.8VNo requirement50 ns
LVCMOS 1.5VNo requirement50 ns
PCINo requirement50 ns
PCIXNo requirement50 ns
GTL+No requirement50 ns
HSTLNo requirement50 ns
SSTL2No requirement50 ns
HSTL3No requirement50 ns
LVDSNo requirement50 ns
LVPECLNo requirement50 ns
Note:
  1. Input Rise/Fall time applies to all inputs, be it clock or data. Inputs have to ramp up/down linearly, in a monotonic way. Glitches or a plateau may cause double clocking. They must be avoided. For output rise/fall time, see the IBIS models for extraction.

The following figure shows the input and output buffer delays.

Figure 2-9. Input Buffer Delays
Figure 2-10. Output Buffer Delays