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Axcelerator Family FPGAs Datasheet
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2
Electrical Specifications
2.3
I/O Specifications
2.3.1
Pin Descriptions
Introduction
1
General Description
2
Electrical Specifications
2.1
Operating Conditions
2.2
Thermal Characteristics
2.3
I/O Specifications
2.3.1
Pin Descriptions
2.3.1.1
Supply Pins
2.3.1.2
User-Defined Supply Pins
2.3.1.3
Global Pins
2.3.1.4
JTAG/Probe Pins
2.3.1.5
Special Functions
2.3.2
User I/Os
2
2.3.3
I/O Banks and Compatibility
2.3.4
User I/O Naming Conventions
2.3.5
I/O Standard Electrical Specifications
2.3.6
I/O Module Timing Characteristics
2.3.7
3.3V LVTTL
2.3.8
2.5V LVCMOS
2.3.9
1.8V LVCMOS
2.3.10
1.5V LVCMOS (JESD8-11)
2.3.11
3.3V PCI, 3.3V PCI-X
2.4
Voltage-Referenced I/O Standards
2.5
Differential Standards
2.6
Module Specifications
2.7
Routing Specifications
2.8
Global Resources
2.9
Axcelerator Clock Management System
2.10
Embedded Memory
2.11
Other Architectural Features
2.12
Programming
3
Package Pin Assignments
4
Revision History
Microchip FPGA Support
Microchip Information
2.3.1 Pin Descriptions
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This section describes the pin descriptions.
