20.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	INTENCLR	7:0				OSC48MRDY			CLKFAIL	XOSCRDY
		15:8					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		23:16
		31:24
0x04	INTENSET	7:0				OSC48MRDY			CLKFAIL	XOSCRDY
		15:8					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		23:16
		31:24
0x08	INTFLAG	7:0				OSC48MRDY			CLKFAIL	XOSCRDY
		15:8					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		23:16
		31:24
0x0C	STATUS	7:0				OSC48MRDY		CLKSW	CLKFAIL	XOSCRDY
		15:8					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		23:16
		31:24
0x10	XOSCCTRL	7:0	ONDEMAND	RUNSTDBY		SWBEN	CFDEN	XTALEN	ENABLE
0x10	XOSCCTRL	15:8	STARTUP[3:0]				AMPGC	GAIN[2:0]
0x12	CFDPRESC	7:0						CFDPRESC[2:0]
0x13	EVCTRL	7:0								CFDEO
0x14	OSC48MCTRL	7:0	ONDEMAND	RUNSTDBY					ENABLE
0x15	OSC48MDIV	7:0					DIV[3:0]
0x16	OSC48MSTUP	7:0						STARTUP[2:0]
0x17	Reserved
0x18	OSC48MSYNCBUSY	7:0						OSC48MDIV
		15:8
		23:16
		31:24
0x1C	DPLLCTRLA	7:0	ONDEMAND	RUNSTDBY					ENABLE
0x1D ... 0x1F	Reserved
0x20	DPLLRATIO	7:0	LDR[7:0]
		15:8					LDR[11:8]
		23:16					LDRFRAC[3:0]
		31:24
0x24	DPLLCTRLB	7:0			REFCLK[1:0]		WUF	LPEN	FILTER[1:0]
		15:8				LBYPASS		LTIME[2:0]
		23:16	DIV[7:0]
		31:24						DIV[10:8]
0x28	DPLLPRESC	7:0							PRESC[1:0]
0x29 ... 0x2B	Reserved
0x2C	DPLLSYNCBUSY	7:0					DPLLPRESC	DPLLRATIO	ENABLE
0x2D ... 0x2F	Reserved
0x30	DPLLSTATUS	7:0							CLKRDY	LOCK
0x31 ... 0x37	Reserved
0x38	CAL48M	7:0			FCAL[5:0]
		15:8							FRANGE[1:0]
		23:16			TCAL[5:0]
		31:24