47.4.4 Sigma-Delta Analog-to-Digital Converter (SDADC) Characteristics

Table 47-8. Operating Conditions(1)
SymbolParametersConditionsMinTypMaxUnit
ResResolutionDifferential mode-16-bits
Single-Ended mode-15-
CLK_SDADCSampling Clock Speed1-6MHz
CLK_SDADC_FSConversion rateCLK_SDADC/4
fsOutput Data RateFree running modeCLK_SDADC_FS / OSR
Single conversion mode

SKPCNT = N

(CLK_SDADC_FS / OSR) x (N+1)
OSROversampling ratioDifferential mode642561024Cycles
VinInput Conversion rangeVREF<VDDANA-0.3V

Differential mode

Gaincorr = 0x1

- VREF-VREFV

Single-Ended mode(3)

Gaincorr = 0x1

0-VREF
VREF>=VDDANA-0.3V

Differential mode

Gaincorr = 0x1

-0.7xVREF-0.7xVREFV

Single-Ended mode(3)

Gaincorr = 0x1

0-0.7xVREF
VrefReference Voltage range 1-VDDANAV
VcomCommon mode voltageDifferential mode0-VDDANAV
CinInput capacitance 0.4250.50.575pF
ZinInput impedanceDifferential mode1/(Cin x CLK_SDADC_FS)kΩ
Single-Ended mode(3)1/(Cin x CLK_SDADC_FS x 2)
Input anti-alias filter recommendation(2)Rext-1.0-kΩ
Cext3.3-10nF
  1. These are based on simulation. These values are not covered by test or characterization.
  2. External Anti-alias filter must be placed in front of each SDADC input to ensure high-frequency signals to not alias into measurement bandwidth. Use capacitors of X5R type for DC measurement. or capacitors of COG or NPO type for AC measurement.
  3. This mode corresponds to a differential mode where the selected AINNx pin is externally grounded.
Table 47-9. SDADC DC Performance: Differential Input Mode. Chopper ON(1)
SymbolParametersConditions (2)MinTypMaxUnit
INLIntegral Non LinearityCLK_SDADC = 3MHz VREF = 1.2V-+/-2.9+/-3.9LSB
CLK_SDADC = 3MHz INT VREF = 5.5V-+/-8.4+/-9.3
DNLDifferential Non LinearityCLK_SDADC = 3MHz VREF = 1.2V-+/-1.5+/-2.1LSB
CLK_SDADC = 3MHz INT VREF = 5.5V-+/-1.7+/-2.3
EgGain ErrorsCLK_SDADC = 3MHz VREF = 1.2V-+/-0.3+/-1.9%
CLK_SDADC = 3MHz INT VREF = 5.5V-+/-0.3+/-1.7
TCgGain DriftCLK_SDADC = 3MHz VREF = 1.2V-0.93.917.5ppm/°C
OffOffset ErrorCLK_SDADC = 3MHz VREF = 1.2V-+/-2.3+/-3.7mV
CLK_SDADC = 3MHz INT VREF = 5.5V-+/-0.3+/-2.4
TcoOffset Error DriftCLK_SDADC = 3MHz VREF = 1.2V-1.40.010.6uV/°C
  1. OSR=256
Table 47-10. SDADC DC Performance: Differential Input Mode. Chopper OFF(1)
SymbolParametersConditions (2)MinTypMaxUnit
INLIntegral Non LinearityCLK_SDADC = 6MHz VREF = 1.2V-+/-5.5+/-9.3LSB
CLK_SDADC = 6MHz INT VREF = 5.5V-+/-8.9+/-10.1
DNLDifferential Non LinearityCLK_SDADC = 6MHz VREF = 1.2V-+/-2.8+/-4.1LSB
CLK_SDADC = 6MHz INT VREF = 5.5V-+/-1.8+/-3
EgGain ErrorsCLK_SDADC = 6MHz VREF = 1.2V-+/-0.6+/-2.1%
CLK_SDADC = 6MHz INT VREF = 5.5V-+/-0.3+/-1.7
TCgGain DriftCLK_SDADC = 6MHz VREF = 1.2V-19.72.220.9ppm/°C
OffOffset ErrorCLK_SDADC = 6MHz VREF = 1.2V-+/-1.7+/-14.3mV
CLK_SDADC = 6MHz INT VREF = 5.5V-+/-4.9+/-13.2
TcoOffset Error DriftCLK_SDADC = 6MHz VREF = 1.2V-1412.460μV/°C
Input noise rmsAC Input noise rmsOSR = 256 VREF = 1.2V-1920
OSR = 256 VREF = 5.5V-5976mVrms
  1. OSR=256
Table 47-11. SDADC AC Performance: : Differential Input Mode(1)
SymbolParametersConditions (2)MinTypMaxUnit
ENOBEffective Number Of BitsExt ref = 1.2V1215.315.4bits
Int Ref = 5.5V12.913.114
DRDynamic RangeExt ref = 1.2V90.592.493.2dB
Int Ref = 5.5V83.095.697.0
SNRSignal to Noise RatioExt ref = 1.2V68.788.789dB
Int Ref = 5.5V8395.697
SINADSignal to Noise + Distortion RatioExt ref = 1.2V71.190.791.7dB
Int Ref = 5.5V77.178.683.2
THDTotal Harmonic DistortionExt ref = 1.2V-102.3-94.6-75.3dB
Int Ref = 5.5V-99.9-94.7-85.4
  1. Values based on characterization.
  2. OSR=256, Chopper OFF, Sampling Clock Speed at 6MHz.