36.8.19 Compare/Capture Channel x

The full offset for this register is 0x44 + n*0x04 [n = 0..3 for TCC0; n = 0,1 for TCC1 and TCC2].

The CCx register represents the 16-bit, 24- bit value, CCx. The register has the following two functions, depending on the mode of operation:

For capture operation, this register represents the second buffer level and access point for the CPU and DMA.

For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.

The CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition occurs.

In addition, in match frequency operation, the CC0 register controls the counter period.

Note: This bit is write-synchronized. SYNCBUSY.CCx must be checked to ensure that CCx synchronization is complete.
Name: CCx
Offset: 0x44 + x*0x04 [x=0..3]
Reset: 0x00000000
Property: Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CC[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CC[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CC[1:0]DITHER[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:6 – CC[17:0] Channel x Compare/Capture Value

These bits hold the value of the Channel x Compare/Capture register.

Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [23:m]
0x0 - NONE 23:0
0x1 - DITH4 23:4
0x2 - DITH5 23:5
0x3 - DITH6 23:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [n:0]
0x0 - NONE -
0x1 - DITH4 3:0
0x2 - DITH5 4:0
0x3 - DITH6 5:0 (depicted)