36.8.22 Period Buffer Value

Note: This bit is write-synchronized. SYNCBUSY.PER must be checked to ensure the PER register synchronization is complete. This register must be written with 32-bit accesses only (no 8-bit or 16-bit writes).
Name: PERBUF
Offset: 0x6C
Reset: 0xFFFFFFFF
Property: Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 PERBUF[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 15141312111098 
 PERBUF[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 76543210 
 PERBUF[1:0]DITHERBUF[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 23:6 – PERBUF[17:0] Period Buffer Value

These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition or CTRLBSET.CMD = UPDATE command when CTRLBSET.LUPD = 1.

Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [23:m]
0x0 - NONE 23:0
0x1 - DITH4 23:4
0x2 - DITH5 23:5
0x3 - DITH6 23:6 (depicted)

Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number

These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is copied to the PER.DITHER bits on an UPDATE condition or CTRLBSET.CMD = UPDATE command when CTRLBSET.LUPD = 1.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [n:0]
0x0 - NONE -
0x1 - DITH4 3:0
0x2 - DITH5 4:0
0x3 - DITH6 5:0 (depicted)