36.8.16 Pattern
Note: This register is write-synchronized: SYNCBUSY.PATT must be
checked to ensure the PATT register synchronization is complete.
| Name: | PATT |
| Offset: | 0x38 |
| Reset: | 0x0000 |
| Property: | Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PGV7 | PGV6 | PGV5 | PGV4 | PGV3 | PGV2 | PGV1 | PGV0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PGE7 | PGE6 | PGE5 | PGE4 | PGE3 | PGE2 | PGE1 | PGE0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVx Pattern Generation Output Value x [x = 7..0]
This register holds the values of pattern for each waveform output.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEx Pattern Generation Output Enable x [x = 7..0]
This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override the corresponding SWAP output with the corresponding PGVx value.