25.4.2.2 External Pin Processing

Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense n (SENSEn) bit field in the CONFIG0 or CONFIG1 register. The corresponding interrupt (EXTINT[n]) flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition is met.

When the interrupt flag has been cleared in Edge-sensitive mode, INTFLAG.EXTINT[n] will only be set if a new interrupt condition is met.

In level-sensitive mode, when the interrupt has been cleared, INTFLAG.EXTINT[n] will be set immediately if the EXTINTn pin still matches the interrupt condition.

Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_OSC32K. Filtering is enabled if the Filter Enable n (FILTENn) bit in the CONFIG0 or CONFIG1 register is written to ‘1’. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_OSC32K and outputs the value when two or more samples are equal.

When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Level detection and asynchronous edge detection do not require GCLK_EIC or CLK_OSC32K and can generate asynchronous interrupts and events.

If filtering or synchronous edge detection is enabled, the EIC automatically requests GCLK_EIC or CLK_OSC32K to operate. The selection between these two clocks is done by writing to the Clock Selection (CKSEL) bit field in the Control A (CTRLA) register. GCLK_EIC must be enabled in the GCLK module. In these modes, the external pin is sampled at the EIC clock rate, thus, pulses with a duration lower than two EIC clock periods may not be properly detected.

Detection latency depends on the detection mode.