20.6.1 Control A
When the Always-On bit in the Control A (CTRLA.ALWAYSON) register is
‘1’, this register will be read-only.
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0xXX |
| Property: | PAC Write-Protection, Enable-Protected, Write-Synchronized |
The Reset value is determined from the Boot Configuration Fuses (BOOTCFG).
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ALWAYSON | WEN | ENABLE | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | x | x | x |
Bit 7 – ALWAYSON Always-On
This bit controls whether the WDT will run continuously or not.
This bit is only cleared by a Reset.
This bit is set by writing a ‘1’ to it.
Writing a ‘0’ to this bit has no effect.
This bit is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.
1’,
the Control A (CTRLA) register, the Configuration (CONFIG) register, and the Early
Warning Control (EWCTRL) register will be read-only, and any writes to these
registers will cause an error. | Value | Description |
|---|---|
| 0 | The WDT can be enabled and disabled through the ENABLE bit |
| 1 | The WDT is enabled and can only be disabled by a Power-on Reset (POR) |
Bit 2 – WEN Watchdog Timer Window Mode Enable
This bit controls whether the Window mode is enabled or not.
This bit is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.
| Value | Description |
|---|---|
| 0 | Window mode is disabled |
| 1 | Window mode is enabled |
Bit 1 – ENABLE Enable
This bit controls whether the WDT is enabled or not.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled or disabled. The value written to CTRL.ENABLE will read back immediately, and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not Enable-Protected.
This bit is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.
| Value | Description |
|---|---|
| 0 | The WDT is disabled |
| 1 | The WDT is enabled |