20.6.3 Early Warning Control
When the Always-On bit in the Control A register (CTRLA.ALWAYSON) is
‘1’, this register will be read-only.
| Name: | EWCTRL |
| Offset: | 0x02 |
| Reset: | 0xXX |
| Property: | PAC Write-Protection |
The Reset value is determined from the Boot Configuration Fuses (BOOTCFG).
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EWOFFSET[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | x | x | x | x | |||||
Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset
This bit field is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.
| Value | Name | Description |
|---|---|---|
| 0x0 | CYC8 | 8 clock cycles |
| 0x1 | CYC16 | 16 clock cycles |
| 0x2 | CYC32 | 32 clock cycles |
| 0x3 | CYC64 | 64 clock cycles |
| 0x4 | CYC128 | 128 clock cycles |
| 0x5 | CYC256 | 256 clock cycles |
| 0x6 | CYC512 | 512 clock cycles |
| 0x7 | CYC1024 | 1024 clock cycles |
| 0x8 | CYC2048 | 2048 clock cycles |
| 0x9 | CYC4096 | 4096 clock cycles |
| 0xA | CYC8192 | 8192 clock cycles |
| 0xB - 0xF | — | Reserved |