20.6.2 Configuration

When the Always-On bit in the Control A register (CTRLA.ALWAYSON) is ‘1’, this register will be read-only.

Name: CONFIG
Offset: 0x01
Reset: 0xXX
Property: PAC Write-Protection

The Reset value is determined from the Boot Configuration Fuses (BOOTCFG).

Bit 76543210 
 WINDOW[3:0]PER[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period

In Window mode, this bit field controls the WDT closed window period as a number of cycles of the 1.024 kHz CLK_WDT_OSC clock.

This bit field is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.

ValueNameDescription
0x0 CYC8 8 clock cycles
0x1 CYC16 16 clock cycles
0x2 CYC32 32 clock cycles
0x3 CYC64 64 clock cycles
0x4 CYC128 128 clock cycles
0x5 CYC256 256 clock cycles
0x6 CYC512 512 clock cycles
0x7 CYC1024 1024 clock cycles
0x8 CYC2048 2048 clock cycles
0x9 CYC4096 4096 clock cycles
0xA CYC8192 8192 clock cycles
0xB CYC16384 16384 clock cycles
Other Reserved

Bits 3:0 – PER[3:0] Time-Out Period

This bit field controls the WDT time-out period as a number of 1.024 kHz CLK_WDT_OSC clock cycles. In Window mode operation, this bit field defines the open window period.

This bit field is loaded from the BOOTCFG – Boot Configuration Fuses section at start-up.

ValueNameDescription
0x0 CYC8 8 clock cycles
0x1 CYC16 16 clock cycles
0x2 CYC32 32 clock cycles
0x3 CYC64 64 clock cycles
0x4 CYC128 128 clock cycles
0x5 CYC256 256 clock cycles
0x6 CYC512 512 clock cycles
0x7 CYC1024 1024 clock cycles
0x8 CYC2048 2048 clock cycles
0x9 CYC4096 4096 clock cycles
0xA CYC8192 8192 clock cycles
0xB CYC16384 16384 clock cycles
Other Reserved