21.8.7 Synchronization Busy

Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: –

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 CLOCKSYNC   MASK0    
Access RR 
Reset 00 
Bit 76543210 
   ALARM0 CLOCKFREQCORRENABLESWRST 
Access RRRRR 
Reset 00000 

Bit 15 – CLOCKSYNC CLOCK Read Resynchronization Enable Synchronization Busy

This bit is cleared when the synchronization of CTRLA.CLOCKSYNC is complete.

This bit is set when the synchronization of CTRLA.CLOCKSYNC is started.

Note: This bit will only be set when writing to CTRLA.CLOCKSYNC, not as a result of ongoing read resynchronization of the CLOCK register.

Bit 11 – MASKn Alarm n Mask Synchronization Busy

This bit is cleared when the synchronization of the MASKn register is complete.

This bit is set when the synchronization of the MASKn register is started.

Bit 5 – ALARMn Alarm n Value Synchronization Busy

This bit is cleared when the synchronization of the ALARMn register is complete.

This bit is set when the synchronization of the ALARMn register is started.

Bit 3 – CLOCK Clock Value Synchronization Busy

This bit is cleared when the synchronization of the CLOCK register is complete.

This bit is set when the synchronization of the CLOCK register is started.

Bit 2 – FREQCORR Frequency Correction Synchronization Busy

This bit is cleared when the synchronization of the FREQCORR register is complete.

This bit is set when the synchronization of the FREQCORR register is started.

Bit 1 – ENABLE Enable Synchronization Busy

This bit is cleared when the synchronization of CTRLA.ENABLE is complete.

This bit is set when the synchronization of CTRLA.ENABLE is started.

Bit 0 – SWRST Software Reset Synchronization Busy

This bit is cleared when the synchronization of CTRLA.SWRST is complete.

This bit is set when the synchronization of CTRLA.SWRST is started.