21.8.1 Control A


Bit	15	14	13	12	11	10	9	8
	CLOCKSYNC				PRESCALER[3:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MATCHCLR	CLKREP			MODE[1:0]		ENABLE	SWRST
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 15 – CLOCKSYNC CLOCK Read Resynchronization Enable

This bit controls the continuous read resynchronization of the CLOCK register.

Note: This bit is not enable-protected.

Value	Description
0	Continuous read resynchronization of CLOCK is disabled. The values in CLOCK are not continuously updated and are invalid.
1	Continuous read resynchronization of CLOCK is enabled. The values in CLOCK are continuously updated and valid.

Bits 11:8 – PRESCALER[3:0] Prescaler

This bit field controls the prescaling factor for the RTC clock source (CLK_RTC_OSC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off.

Note: This bit field is not synchronized.

Value	Name	Description
0x0	OFF	CLK_RTC_CNT = GCLK_RTC/1
0x1	DIV1	CLK_RTC_CNT = GCLK_RTC/1
0x2	DIV2	CLK_RTC_CNT = GCLK_RTC/2
0x3	DIV4	CLK_RTC_CNT = GCLK_RTC/4
0x4	DIV8	CLK_RTC_CNT = GCLK_RTC/8
0x5	DIV16	CLK_RTC_CNT = GCLK_RTC/16
0x6	DIV32	CLK_RTC_CNT = GCLK_RTC/32
0x7	DIV64	CLK_RTC_CNT = GCLK_RTC/64
0x8	DIV128	CLK_RTC_CNT = GCLK_RTC/128
0x9	DIV256	CLK_RTC_CNT = GCLK_RTC/256
0xA	DIV512	CLK_RTC_CNT = GCLK_RTC/512
0xB	DIV1024	CLK_RTC_CNT = GCLK_RTC/1024
Other	—	Reserved

Bit 7 – MATCHCLR Clear on Match

This bit controls whether the counter is cleared on a match.

Note: This bit is not synchronized.

Value	Description
0	The counter is not cleared on a Compare/Alarm match
1	The counter is cleared on a Compare/Alarm match

Bit 6 – CLKREP Clock Representation

This bit determines how the hours are represented in the Clock Value (CLOCK) register.

Note: This bit is not synchronized.

Value	Name	Description
0	CLK24H	24 hour clock format
1	CLK12H	12 hour (AM/PM) clock format

Bits 3:2 – MODE[1:0] Operating Mode

This bit field controls the operating mode of the RTC.

Note: This bit field is not synchronized.

Value	Name	Description
0x0	COUNT32	Mode 0: 32-bit counter
0x1	COUNT16	Mode 1: 16-bit counter
0x2	CLOCK	Mode 2: Clock/calendar
Other	—	Reserved

Bit 1 – ENABLE Enable

This bit controls whether the RTC is enabled.

Due to synchronization, there is a delay from writing to CTRLA.ENABLE until the RTC is enabled or disabled. The value written to CTRLA.ENABLE will be read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

Note: This bit is not enable-protected.

Value	Description
0	The RTC is or being disabled
1	The RTC is or being enabled

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled.

Due to synchronization, there is a delay from writing to CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

Note:

This bit is not enable protected.
Writing a ‘1’ to CTRL.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.
The RTC should be disabled before the RTC is reset to avoid undefined behavior.

Value	Description
0	There is no reset operation ongoing
1	The reset operation is ongoing

Name:	CTRLA
Offset:	0x00
Reset:	0x0000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized