23.4.2.5 Double Buffering

The Pattern (PATT), Period (PER) and Compare Channels (CCn) registers are all double buffered. Each buffer register has a buffer valid bit in the Status register (STATUS), which indicates that the buffer register contains a valid value that can be copied into the corresponding register. As long as the respective Buffer Valid Status flag (PATTBUFV, PERBUFV or CCBUFVx) are set to '1', and the related SYNCBUSY bits are set (SYNCBUSY.PATT, SYNCBUSY.PER or SYNCBUSY.CCn), a write to the respective PATT/PATTBUF, PER/PERBUF or CCn/CCBUFx registers will generate a PAC error, and read access to the respective PATT, PER or CCn register is invalid.

When a Buffer Valid Flag bit in the STATUS register is '1' and the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD) is cleared, double buffering is enabled: The data from the buffer registers will be copied into the corresponding register under hardware UPDATE conditions, and then the Buffer Valid Flag bit in the STATUS register are automatically cleared by hardware. The buffer valid flag bits in the STATUS register can be cleared manually, but they must be cleared twice successively.

Note: A software update command issued by writing the UPDATE command value to the TCC Command bit field in the Control B Set register (CTRLBSET.CMD) acts independently of LUPD value.

A compare register is double buffered as shown in the following figure.

Figure 23-10. Compare Channel Double Buffering

Both the registers (PATT, PER, and CCn) and the corresponding buffer registers (PATTBUF, PERBUF, and CCBUFx) are available in the I/O register map, and the double buffering feature is not mandatory. Double buffering is disabled by writing a '1' to the Lock Update bit in the Control B Set register (CTRLBSET.LUPD).

Note: When NFRQ, MFRQ or PWM down-counting counter mode (with the Counter Direction bit in the Control B Clear or Set registers (CTRLBCLR/SET.DIR) set) is enabled and double buffering is enabled (CTRLBCLR/SET.LUPD is cleared), the PERBUF register is continuously copied into the PER independently of update conditions.

Figure 23-11. Unbuffered Single-Slope Up-Counting Operation

Figure 23-12. Unbuffered Single-Slope Down-Counting Operation

A counter wraparound can occur in any operation mode when up-counting without buffering. COUNT and TOP are continuously compared, so when a new value that is lower than the current COUNT is written to TOP, COUNT will wrap before a compare match occurs.

Figure 23-13. Unbuffered Dual-Slope Operation

When double buffering is used, the buffer can be written at any time, and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in the following figure. This prevents wraparound and the generation of irregular waveforms.

Figure 23-14. Changing the Period Using Buffering