24.6.2 Channel Status
| Name: | CHSTATUS |
| Offset: | 0x0C |
| Reset: | 0x0000000F |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHBUSY3 | CHBUSY2 | CHBUSY1 | CHBUSY0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| USRRDY3 | USRRDY2 | USRRDY1 | USRRDY0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 1 | 1 | 1 | 1 |
Bits 16, 17, 18, 19 – CHBUSYn Channel n Busy
This bit is cleared when channel n is idle.
This bit is set if an event on channel n has not been handled by all event users connected to channel n. Refer to Event System Channel for further information.
Note: When the event channel path is
asynchronous, this bit will always read as ‘
0’Bits 0, 1, 2, 3 – USRRDYn Users Ready on Channel n
This bit is cleared when at least one of the event users connected to channel n is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events. Refer to Event System Channel for further information.
Note: When the event channel path is
asynchronous, this bit will always read as ‘
0’