24.6.3 Interrupt Enable Clear

This register allows the user to disable an interrupt without performing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).

Name:	INTENCLR
Offset:	0x10
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					EVD3	EVD2	EVD1	EVD0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
					OVR3	OVR2	OVR1	OVR0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 16, 17, 18, 19 – EVDn Event Detected Channel n Interrupt Enable

Writing a ‘0’ to this bit has no effect. 

Writing a ‘1’ to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt.

Value	Description
0	The Event Detected Channel n interrupt is disabled
1	The Event Detected Channel n interrupt is enabled

Bits 0, 1, 2, 3 – OVRn Overrun Channel n Interrupt Enable

Writing a ‘0’ to this bit has no effect. 

Writing a ‘1’ to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt.

Value	Description
0	The Overrun Channel n interrupt is disabled
1	The Overrun Channel n interrupt is enabled