24.6.5 Interrupt Flag Status and Clear


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					EVD3	EVD2	EVD1	EVD0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
					OVR3	OVR2	OVR1	OVR0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 16, 17, 18, 19 – EVDn Event Detected Channel n

This flag is cleared by writing a ‘1’ to it.

This flag is set on the next CLK_EVSYS_APB cycle after an event is propagated through the channel, and an interrupt request will be generated if INTENSET.EVDn is ‘1’. Refer to Channel Event Detection for further information.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Event Detected Channel x interrupt flag.

Note: When the event channel path is asynchronous, the EVDn interrupt flag will not be set.

Bits 0, 1, 2, 3 – OVRn Overrun Channel n

This flag is cleared by writing a ‘1’ to it.

This flag is set on the next CLK_EVSYS_APB cycle after an overrun channel condition occurs, and an interrupt request will be generated if INTENSET.OVRn is ‘1’. Refer to Overrun Channel Detection for further information.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Overrun Detected Channel n interrupt flag.

Note: When the event channel path is asynchronous, the OVRn interrupt flag will not be set.

Name:	INTFLAG
Offset:	0x18
Reset:	0x00000000
Property:	–